In EEPROM arrays, high voltages are generated on chip for programming purposes. These high voltages (e.g., 20 volts) are much higher than the highest operating voltage (e.g., 3 volts), and are typically produced by charge pumps. Because these charge pumps consume power and circuit area, it is desirable to minimize the total capacitance that these high voltage generators drive.
In CMOS integrated circuits, PMOS transistors are used in pull up circuits while NMOS transistors are used in pull down circuits. However, PMOS transistors in a CMOS integrated circuit must be electrically isolated in an N-well. This N-well must be biased at or above the high supply voltage to guarantee that the P/N junction, formed by the P-type drain/source regions of the PMOS transistors and the N-well, are not forward-biased. If PMOS transistors are used in the high-voltage subcircuits, these N-type isolation wells constitute a very large capacitance for the on-chip high voltage generator to drive. Moreover, the N-type isolation well itself increases area and adds process complexity.
Since NMOS transistors can be fabricated on a P-type substrate, such NMOS transistors require no isolation well. Therefore, in high-voltage subcircuits supplied by on-chip high-voltage generators, the use of NMOS transistors is typically preferable to the use of PMOS transistors.
However, the lowest conducting source-drain voltage of an NMOS transistor is limited by the transistor's threshold voltage ("Vt"). Thus, if a high voltage needs to pass from the drain to source, then the gate voltage must be at least one Vt higher than the drain voltage.
A conventional circuit 100 which is used to pass a high voltage Vpp is illustrated in FIG. 1. The circuits of the kind illustrated in FIG. 1 are important in NAND flash memory applications, especially for decoding circuits such as block and row decoders and high-voltage multiplexers.
The circuit in FIG. 1 has drawbacks. The first drawback is that the circuit performance is degraded as the supply voltage Vcc decreases. Moreover, the circuit is inoperative when the supply voltage Vcc is less than the sum of the threshold voltages VtM2 and VtM3 of transistors M2 and M3, respectively. In order to pass Vpp to word line WL, node B (attached to the gate of M3) must be boosted to Vpp+VtM3. In order for node B to be boosted to Vpp+VtM3, node A must be boosted to Vpp+VtM3+VtM2. With supply voltages Vcc around 3V, and threshold voltages above 1.5 volts due to the body effect, the circuit in FIG. 1 does not function properly.
In order to boost node A to Vpp+VtM3+VtM2, the following inequality of Equation (1) must hold in which CA is the total parasitic capacitance of node A, and C is the capacitance of capacitor C. EQU Vcc*C/(C+CA).gtoreq.VtM2+VtM3 (1)
In order for the circuit in FIG. 1 to function with low supply voltages Vcc less than or equal to 3V, transistors M2 and M3 must have very low threshold voltages VtM2 and VtM3. However, the various manners of lowering the threshold voltage of a transistor all result in larger leakage currents from source to drain when the transistor is off.
Another way to satisfy the above inequality is to increase the coupling ratio C/(C+CA) by increasing the coupling capacitor C. However, capacitors are fairly large circuit elements and increasing C increases circuit area.
Typically, the high voltage pass gate M3 of FIG. 1 is used to drive word lines of a memory array during a high-voltage operation such as programming. The memory array may have many thousands of word lines. Often only one word line is programmed while all the other word lines are not programmed. In this case, only one of the word lines in the selected block is raised to Vpp while the other fifteen word lines in the selected block are raised to approximately ten volts; more importantly, the word lines in all of the unselected blocks are left floating. If transistor M3 is made to be a low threshold device and is replicated once for each word line, the sum of the leakage currents in all of the words in the unselected blocks will be very high, thus placing high current demands on the high voltage charge pump, wasting a large amount of power, and slowing the rise time of the charge pump voltage.
As is apparent from the above discussion, a need exists for a block decoder having small circuit area, low leakage current, fast control of high voltage pass transistors, and low supply voltage capability.